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preliminary 3.3v 64k x 18 synchronous quadport? static ram cy7c0430v cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 november 18, 1999 30v features ? true four-ported memory cells which allow simulta- neous access of the same memory location synchronous pipelined device ? 64k x 18 organization pipelined output mode allows fast 133-mhz operation high bandwidth up to 10 gbps (133 mhz x 18 bits wide x 4 ports) 0.25-micron cmos for optimum speed/power high-speed clock to data access 4.7 ns (max.) 3.3v low operating power ? active = 750ma (maximum) ? standby = 1ma (maximum) counter wrap-around control ? internal mask register controls counter wrap-around ? counter-interrupt flags to indicate wrap-around counter readback on address lines mask register readback on address lines interrupt flags for message passing master reset for all ports width and depth expansion capabilities dual chip enables on all ports for easy depth expansion separate upper-byte and lower-byte controls on all ports 272-bga package (27 mm x 27 mm 1.27 mm ball pitch) commercial and industrial temperature ranges ieee 1149.1 jtag boundary scan bist (built in self test) controller notes: 1. port 1 control logic block is detailed on page 2. 2. port 2, port 3, and port 4 logic blocks are similar to port 1 logic blocks. port-1 control logic port 1 counter/ mask reg/ address decode port 1 i/o 18 top level logic block diagram ram array port 1 operation-control logic blocks [1] port 2 logic blocks [2] port 4 logic blocks [2] port 3 logic blocks [2] cntld p1 cntinc p1 cntrst p1 mkld p1 cntint p1 mkrd p1 cntrd p1 int p1 ce 1p1 ce 0p1 r/w p1 oe p1 ub p1 lb p1 i/o 0p1 - i/o 17p1 a 0p1 ?a 15p1 16 tms tck tdi tdo bist mrst reset logic jtag controller clk p1 clk p1 clkbist port 1 port 2 port 3 port 4 for the most recent information, visit the cypress web site at www.cypress.com
cy7c0430v preliminary 2 addr. read back port 1 operation-control logic block diagram: r/w p1 ce 0p1 ce 1p1 lb p1 oe p1 ub p1 i/o 9p1 ? i/o 17p1 i/o 0p1 ? i/o 8p1 i/o control counter/ a 0p1 ? a 15p1 clk p1 cntld p1 cntinc p1 cntrst p1 16 9 9 mkld p1 cntint p1 mkrd p1 mask register port-1 port 1 port 1 ram array port 1 port 2 po r t 4 p ort 3 address register readback register port 1 cntrd p1 port 1 address decode port 1 interrupt logic r/w p1 ce 0p1 ce 1p1 oe p1 int p1 clk p1 mrst mrst priority decision logic mrst (address readback is independent of ces) w r lb p1 ub p1
cy7c0430v preliminary 3 functional description the cy7c0430v is a 1-mb synchronous true four-port static ram. this is a high-speed, low-power 3.3v cmos dual-port static ram. four ports are provided, permitting independent, simultaneous access for reads from any location in memory. a particular port can write to a certain location while other ports are reading that location simultaneously. the result of writing to the same location by more than one port at the same time is undefined. registers on control, address and data lines al- low for minimal set-up and hold time. data is registered for decreased cycle time. clock to data valid t cd2 = 4.7 ns. each port contains a burst counter on the input address register. after externally loading the counter with the initial address the counter will self-increment the address in- ternally (more details to follow). the internal write pulse width is independent of the duration of the r/w input signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. one cycle is required with chip enables asserted to reac- tivate the outputs. counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. a port's burst counter is loaded with an external address when the port's counter load pin (cntld ) is asserted low. when the port's counter increment pin (cntinc ) is asserted, the address counter will increment on each subsequent low-to- high transition of that port's clock signal. this will read/write one word from/into each successive address location until cntinc is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. a counter-mask register is used to control the counter wrap. the counter and mask register operations are described in more details in the following sections. the counter or mask register values can be read back on the bidirectional address lines by activating mkrd or cntrd re- spectively. the new features added to the quadport ? as compared to standard synchronous dual-ports include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, readback of mask register value on address lines, interrupt flags for message passing, bist, jtag for boundary scan, and asynchronous master reset.
cy7c0430v preliminary 4 pin configuration 272-ball grid array (bga) top view 1234567891011121314151617181920 a lb p1 i/o17 p2 i/o15 p2 i/o13 p2 i/o11 p2 i/o9 p2 i/o16 p1 i/o14 p1 i/o12 p1 i/o10 p1 i/o10 p4 i/o12 p4 i/o14 p4 i/o16 p4 i/o9 p3 i/o11 p3 i/o13 p3 i/o15 p3 i/o17 p3 lb p4 b vdd1 ub p1 i/o16 p2 i/o14 p2 i/o12 p2 i/o10 p2 i/o17 p1 i/o13 p1 i/o11 p1 tms tdi i/o11 p4 i/o13 p4 i/o17 p4 i/o10 p3 i/o12 p3 i/o14 p3 i/o16 p3 ub p4 vdd1 c a14 p1 a15 p1 ce1 p1 ce0 p1 r/w p1 i/o15 p1 vss2 vss2 i/o9 p1 tck tdo i/o9 p4 vss2 vss2 i/o15 p4 r/w p4 ce0 p4 ce1 p4 a15 p4 a14 p4 d vss1 a12 p1 a13 p1 oe p1 vdd2 vss2 vss2 vdd2 vdd vss vss vdd vdd2 vss2 vss2 vdd2 oe p4 a13 p4 a12 p4 vss1 e a10 p1 a11 p1 mkrd p1 cntrd p1 cntrd p4 mkrd p4 a11 p4 a10 p4 f a7 p1 a8 p1 a9 p1 cntint p1 cntint p4 a9 p4 a8 p4 a7 p4 g vss1 a5 p1 a6 p1 cntinc p1 cntinc p4 a6 p4 a5 p4 vss1 h a3 p1 a4 p1 mkld p1 cntld p1 cntld p4 mkld p4 a4 p4 a3 p4 j vdd1 a1 p1 a2 p1 vdd gnd [3] gnd [3] gnd [3] gnd [3] vdd a2 p4 a1 p4 vdd1 k a0 p1 int p1 cntrst p1 clk p1 gnd [3] gnd [3] gnd [3] gnd [3] clk p4 cntrst p4 int p4 a0 p4 l a0 p2 int p2 cntrst p2 vss gnd [3] gnd [3] gnd [3] gnd [3] vss cntrst p3 int p3 a0 p3 m vdd1 a1 p2 a2 p2 clk p2 gnd [3] gnd [3] gnd [3] gnd [3] clk p3 a2 p3 a1 p3 vdd1 n a3 p2 a4 p2 mkld p2 cntld p2 cntld p3 mkld p3 a4 p3 a3 p3 p vss1 a5 p2 a6 p2 cntinc p2 cntinc p3 a6 p3 a5 p3 vss1 r a7 p2 a8 p2 a9 p2 cntint p2 cntint p3 a9 p3 a8 p3 a7 p3 t a10 p2 a11 p2 mkrd p2 cntrd p2 cntrd p3 mkrd p3 a11 p3 a10 p3 u vss1 a12 p2 a13 p2 oe p2 vdd2 vss2 vss2 vdd2 vdd vss vss vdd vdd2 vss2 vss2 vdd2 oe p3 a13 p3 a12 p3 vss1 v a14 p2 a15 p2 ce1 p2 ce0 p2 r/w p2 i/o6 p2 vss2 vss2 i/o0 p2 nc nc i/o0 p3 vss2 vss2 i/o6 p3 r/w p3 ce0 p3 ce1 p3 a15 p3 a14 p3 w vdd1 ub p2 i/o7 p1 i/o5 p1 i/o3 p1 i/o1 p1 i/o8 p2 i/o4 p2 i/o2 p2 mrst clkbist i/o2 p3 i/o4 p3 i/o8 p3 i/o1 p4 i/o3 p4 i/o5 p4 i/o7 p4 ub p3 vdd1 y lb p2 i/o8 p1 i/o6 p1 i/o4 p1 i/o2 p1 i/o0 p1 1/o7 p2 i/o5 p2 i/o3 p2 i/o1 p2 i/o1 p3 i/o3 p3 i/o5 p3 i/o7 p3 i/o0 p4 i/o2 p4 i/o4 p4 i/o6 p4 i/o8 p4 lb p3 note: 3. central leads are for thermal dissipation only. they are connected to device v ss .
cy7c0430v preliminary 5 selection guide cy7c0430v -133 cy7c0430v -100 f max2 (mhz) 133 100 max access time (ns) (clock to data) 4.7 5.0 max operating current i cc (ma) 750 600 max standby current for i sb1 (ma) (all ports ttl level) 200 150 max standby current for i sb3 (ma) (all ports cmos level) 1.0 1.0 pin definitions port 1 port 2 port 3 port 4 description a 0p1 ? a 15p1 a 0p2 ? a 15p2 a 0p3 ? a 15p3 a 0p4 ? a 15p4 address input/output. i/o 0p1 ? i/o 17p1 i/o 0p2 ? i/o 17p2 i/o 0p3 ? i/o 17p3 i/o 0p4 ? i/o 17p4 data bus input/output. clk p1 clk p2 clk p3 clk p4 clock input. this input can be free running or strobed. maximum clock input rate is f max . lb p1 lb p2 lb p3 lb p4 lower byte select input. asserting this signal low en- ables read and write operations to the lower byte. for read operations both the lb and oe signals must be as- serted to drive output data on the lower byte of the data pins. ub p1 ub p2 ub p3 ub p4 upper byte select input. same function as lb , but to the upper byte. ce 0p1 ,ce 1p1 ce 0p2 ,ce 1p2 ce 0p3 ,ce 1p3 ce 0p4 ,ce 1p4 chip enable input. to select any port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). oe p1 oe p2 oe p3 oe p4 output enable input. this signal must be asserted low to enable the i/o data lines during read operations. oe is asynchronous input. r/w p1 r/w p2 r/w p3 r/w p4 read/write enable input. this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. mrst master reset input. this is one signal for all ports. mrst is an asynchronous input. asserting mrst low per- forms all of the reset functions as described in the text. a mrst operation is required at power-up. cntrst p1 cntrst p2 cntrst p3 cntrst p4 counter reset input. asserting this signal low resets the burst address counter of its respective port to zero. cntrst is second to mrst in priority with respect to counter and mask register operations. mkld p1 mkld p2 mkld p3 mkld p4 mask register load input. asserting this signal low loads the mask register with the external address avail- able on the address lines. mkld operation has higher priority over cntld operation. cntld p1 cntld p2 cntld p3 cntld p4 counter load input. asserting this signal low loads the burst counter with the external address present on the address pins. cntinc p1 cntinc p2 cntinc p3 cntinc p4 counter increment input. asserting this signal low in- crements the burst address counter of its respective port on each rising edge of clk.
cy7c0430v preliminary 6 cntrd p1 cntrd p2 cntrd p3 cntrd p4 counter readback input. when asserted low, the inter- nal address value of the counter will be read back on the address lines. during cntrd operation, both cntld and cntinc must be high. counter readback operation has higher priority over mask register readback opera- tion. counter readback operation is independent of port chip enables. if address readback operation occurs with chip enables active (ce 0 = low, ce 1 = high), the data lines (i/os) will be three-stated. the readback timing will be valid after one no-operation cycle plus t cd2 from the rising edge of the next cycle. mkrd p1 mkrd p2 mkrd p3 mkrd p4 mask register readback input. when asserted low, the value of the mask register will be readback on address lines. during mask register readback operation, all counter and mkld inputs must be high (see counter and mask register operations truth table). mask register readback operation is independent of port chip enables. if address readback operation occurs with chip enables active (ce 0 = low, ce 1 = high), the data lines (i/os) will be three-stated. the readback will be valid after one no-operation cycle plus t cd2 from the rising edge of the next cycle. cntint p1 cntint p2 cntint p3 cntint p4 counter interrupt flag output. flag is asserted low for one clock cycle when the counter wraps around to loca- tion zero. int p1 int p2 int p3 int p4 interrupt flag output. interrupt permits communications between all four ports. the upper four memory locations can be used for message passing. example of operation: int p4 is asserted low when another port writes to the mailbox location of port 4. flag is cleared when port 4 reads the contents of its mailbox. the same operation is applicable to ports 1, 2, and 3. tms jtag test mode select input. it controls the advance of jtag tap state machine. state machine transitions oc- cur on the rising edge of tck. tck jtag test clock input. this can be clk of any port or an external clock connected to the jtag tap. tdi jtag test data input. this is the only data input. tdi inputs will shift data serially in to the selected register. tdo jtag test data output. this is the only data output. tdo transitions occur on the falling edge of tck. tdo normal- ly three-stated except when captured data is shifted out of the jtag tap. clkbist bist clock input. gnd thermal ground for heat dissipation. v ss ground input. v dd power input. v ss1 address lines ground input. v dd1 address lines power input. v ss2 data lines ground input. v dd2 data lines power input. pin definitions (continued) port 1 port 2 port 3 port 4 description
cy7c0430v preliminary 7 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................ ? 65 c to + 150 c ambient temperature with power applied ............................................ ? 55 c to + 125 c supply voltage to ground potential .............. ? 0.5v to + 4.6v dc voltage applied to outputs in high z state............................ ? 0.5v to v cc +0.5v dc input voltage ..................................... ? 0.5v to v cc +0.5v output current into outputs (low)............................. 20 ma static discharge voltage ........................................... >2001v latch-up current ..................................................... >200 ma operating range range ambient temperature v dd commercial 0 c to +70 c 3.3v 150 mv industrial ? 40 c to +85 c 3.3v 150 mv electrical characteristics over the operating range parameter description cy7c0430v unit -133 -100 min. typ max min. typ max v oh output high voltage (v cc = min., i oh = ? 4.0 ma) 2.4 2.4 v v ol output low voltage (v cc = min., i oh = +4.0 ma) 0.4 0.4 v v ih input high voltage 2.0 2.0 v v il input low voltage 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled indust. 413 750 330 600 ma com ? l. ma i sb1 standby current (4 ports toggling at ttl levels,0 active) ce 1-4 v ih , f = f max indust. 80 200 60 150 ma com ? l. ma i sb2 standby current (4 ports toggling at ttl levels, 1 active) ce 1 | ce 2 | ce 3 | ce 4 < v ih , f = f max indust. 170 349 128 263 ma com ? l. ma i sb3 standby current (4 ports cmos level, 0 active) ce 1-4 v ih , f = 0 indust. 0.5 1 0.5 1 ma com ? l. a i sb4 standby current (3 ports cmos level, 1 port ttl active) ce 1 | ce 2 | ce 3 | ce 4 < v ih , f = f max indust. 110 200 83 151 ma com ? l. ma jtag tap electrical characteristics over the operating range parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 4.0 ma 2.4 v v ol1 output low voltage i ol = 4.0 ma 0.4 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i x input leakage current gnd v i v dd ? 100 100 a capacitance parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out output capacitance 8 pf
cy7c0430v preliminary 8 ac test load note: 4. test conditions: c = 10 pf. v th =1.5v output c (a) normal load r = 50 ? z 0 = 50 ? [4] 3.0v gnd 90% 90% 10% t r t f 10% all input pulses (b) three-state delay v th =1.5v output 5 pf r = 50 ? z 0 = 50 ? (c) tap load tdo c= 10 pf z 0 =50 ? gnd 1.5v 50 ?
cy7c0430v preliminary 9 switching characteristics over the industrial operating range parameter description cy7c0430v unit ? 133 ? 100 min. max. min. max. f max2 maximum frequency 133 100 mhz t cyc2 clock cycle time 7.5 10 ns t ch2 clock high time 3 4 ns t cl2 clock low time 3 4 ns t r clock rise time 2 3 ns t f clock fall time 2 3 ns t sa address set-up time 2.5 3 ns t ha address hold time 0.5 0.5 ns t sc chip enable set-up time 2.5 3 ns t hc chip enable hold time 0.5 0.5 ns t sw r/w set-up time 2.5 3 ns t hw r/w hold time 0.5 0.5 ns t sd input data set-up time 2.5 3 ns t hd input data hold time 0.5 0.5 ns t sb byte set-up time 2.5 3 ns t hb byte hold time 0.5 0.5 ns t scld cntld set-up time 2.5 3 ns t hcld cntld hold time 0.5 0.5 ns t scinc cntinc set-up time 2.5 3 ns t hcinc cntinc hold time 0.5 0.5 ns t scrst cntrst set-up time 2.5 3 ns t hcrst cntrst hold time 0.5 0.5 ns t scrd cntrd set-up time 2.5 3 ns t hcrd cntrd hold time 0.5 0.5 ns t smld mkld set-up time 2.5 3 ns t hmld mkld hold time 0.5 0.5 ns t smrd mkrd set-up time 2.5 3 ns t hmrd mkrd hold time 0.5 0.5 ns t oe output enable to data valid 6.5 8 ns t olz [5] oe to low z 1 1 ns t ohz [5] oe to high z 1 6 1 7 ns t cd2 clock to data valid 4.7 5 ns t ca2 clock to counter address readback valid 4.7 5 ns t cm2 clock to mask register readback valid 4.7 5 ns t dc data output hold after clock high 1 1 ns t ckhz [6] clock high to output high z 1 4.8 1 6.8 ns t cklz [6] clock high to output low z 1 1 ns t sint clock to int set time 1 6.5 1 8 ns t rint clock to int reset time 1 6.5 1 8 ns t scint clock to cntint set time 1 6.5 1 8 ns t rcint clock to cntint reset time 1 6.5 1 8 ns
cy7c0430v preliminary 10 notes: 5. this parameter is guaranteed by design, but it is not production tested. 6. valid for both address and data outputs. master reset timing t rs master reset pulse width 7.5 10 ns t rss master reset set-up time 6.0 8.5 ns t rsr master reset recovery time 7.5 10 ns t rsf master reset to interrupt flag reset time 6.5 8 ns t rscntint master reset to counter interrupt flag reset time 6.5 8 port to port delays t ccs clock to clock set-up time 6.5 9 ns switching characteristics over the industrial operating range (continued) parameter description cy7c0430v unit ? 133 ? 100 min. max. min. max.
cy7c0430v preliminary 11 jtag timing and switching waveforms parameter description cy7c0430v unit ? 133 ? 100 min. max. min. max. f jtag maximum jtag tap controller frequency 10 10 mhz t tcyc tck clock cycle time 100 100 ns t th tck clock high time 40 40 ns t tl tck clock low time 40 40 ns t tmss tms setup to tck clock rise 10 10 ns t tmsh tms hold after tck clock rise 10 10 ns t tdis tdi setup to tck clock rise 10 10 ns t tdih tdi hold after tck clock rise 10 10 ns t tdov tck clock low to tdo valid 20 20 ns t tdox tck clock low to tdo invalid 0 0 ns test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov
cy7c0430v preliminary 12 switching waveforms master reset read cycle [7, 8, 9, 10, 11] notes: 7. oe is asynchronously controlled; all other inputs (excluding mrst ) are synchronous to the rising clock edge. 8. cntld = v il , mkld = v ih , cntinc = x, and mrst =cntrst = v ih . 9. the output is disabled (high-impedance state) by ce =v ih following the next rising edge of the clock. 10. addresses do not have to be accessed sequentially. note 8 indicates that address is constantly loaded on the rising edge of the clk. numbers are for reference only. 11. ce is internal signal. ce = vil if ce 0 = v il and ce 1 = v ih . mrst t rsr t rs inactive active tms tdo int cntint t rsf t rss all address/ data lines all other inputs t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency lb ub t sb t hb
cy7c0430v preliminary 13 bank select read [12, 13] read-to-write-to-read (oe = v il ) [14, 15, 16, 17] notes: 12. in this depth expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress quadport device from this data sheet. address (b1) = address (b2) . 13. lb = ub = oe = cntld = v il ; mrst = cntrst = mkld = v ih . 14. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 15. lb = ub = cntld = v il ; mrst = cntrst = mkld =v ih . 16. addresses do not have to be accessed sequentially since cntld = v il constantly loads the address on the rising edge of the clk; numbers are for reference only. 17. during ? no operation, ? data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3
cy7c0430v preliminary 14 read-to-write-to-read (oe controlled) [14, 15, 16, 17] read with address counter advance [18, 19] notes: 18. ce 0 = oe = lb = ub = v il ; ce 1 = r/w = cntrst = mrst = mkld = mkrd = cntrd = v ih . 19. the ? internal address ? is equal to the ? external address ? when cntld = v il . switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 q n clk ce r/w address data in data out oe t cklz t cd2 q n+4 counter hold read with counter t sa t ha t scld t hcld t scinc t hcinc t ch2 t cl2 t cyc2 q x ? 1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address cntld data out cntinc a n
cy7c0430v preliminary 15 write with address counter advance [19, 20] note: 20. ce 0 = lb = ub = r/w = v il ; ce 1 = cntrst = mrst = mkld = mkrd = cntrd = v ih. switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cntinc cntld data in address t sa t ha
cy7c0430v preliminary 16 counter reset [16, 21, 22] notes: 21. ce 0 = lb = ub = v il ; ce 1 = mrst = mkld = mkrd = cntrd = v ih . 22. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cntinc cntld data in address cntrst r/w data out q 0 q 1 q n d 0 a x a 0 a 1 a n a n+1 t scrst t hcrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n t scld t hcld
cy7c0430v preliminary 17 load and read address counter [23] notes: 23. ce 0 = oe = lb = ub = v il ; ce 1 = r/w = cntrst = mrst = mkld = mkrd = v ih . 24. address in output mode. host must not be driving address bus after time t cklz in next clock cycle. 25. address in input mode. host can drive address bus after t ckhz . 26. this is the value of the address counter being read out on the address lines. switching waveforms (continued) read data with counter t sa t ha t scld t hcld t scinc t hcinc t ch2 t cl2 t cyc2 q x ? 1 q x q n q n+1 q n+2 read internal address clk a 0 -a 15 cntld data out cntinc a n t scrd t hcrd cntrd a n a n+1 a n+2 internal address a n+2 a n+2 a n+2 q n+2 t cd2 t dc t cklz t cklz t ckhz t ckhz t ca2 load external address note 24 note 25 [ 26 ]
cy7c0430v preliminary 18 load and read mask register [27] notes: 27. ce 0 = oe = lb = ub = v il ; ce 1 = r/w = cntrst = mrst = cntld = cntrd = cntinc =v ih . 28. this is the value of the mask register read out on the address lines. switching waveforms (continued) t sa t ha t smld t hmld t ch2 t cl2 t cyc2 read mask-register value clk a 0 -a 15 mkld a n t smrd t hmrd mkrd a n a n a n internal value a n a n a n t cklz t ckhz t ca2 load mask register value mask [28] note 24 note 25 a n+2
cy7c0430v preliminary 19 port 1 write to port 2 read [29, 30, 31] notes: 29. ce 0 = oe = lb = ub = cntld =v il ; ce 1 = cntrst = mrst = mkld = mkrd = cntrd = cntinc =v ih . 30. this timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. if t ccs is violated, indeterminate data will be read out. 31. if t ccs < minimum specified value, then port 2 will read the most recent data (written by port 1) only (2*t cyc2 + t cd2 ) after the rising edge of port 2's clock. if t ccs > minimum specified value, then port 2 will read the most recent data (written by port 1) (t cyc2 + t cd2 ) after the rising edge of port 2's clock. switching waveforms (continued) t sa t ha t sw t hw t ch2 t cl2 t cyc2 clk p1 r/w p1 a n d n t ckhz t hd t sa a n t ha q n t dc t ccs t sd t cklz t ch2 t cl2 t cyc2 t cd2 port-1 address port-1 data in clk p2 r/w p2 port-2 address port-2 data out
cy7c0430v preliminary 20 counter interrupt [32, 33, 34] mailbox interrupt timing [35, 36, 37, 38, 39] notes: 32. ce 0 = oe = lb = ub = v il ; ce 1 = r/w = cntrst = mrst = cntrd = mkrd = v ih . 33. cntint is always driven. 34. cntinc goes low as the counter address masked portion is incremented from xx7fh to xx00h. the ? x ? is ? don ? t care. ? 35. ce 0 = oe = lb = ub = cntld =v il ; ce 1 = cntrst = mrst = cntrd = cntinc = mkrd = mkld =v ih . 36. address ? fffe ? is the mailbox location for port 2. 37. port 1 is configured for write operation, and port 2 is configured for read operation. 38. port 1 and port 2 are used for simplicity. all four ports can write to or read from any mailbox. 39. interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of th e read clock. switching waveforms (continued) t smld t hmld t scld t hcld t ch2 t cl2 t cyc2 clk mkld cntld a n xx7eh internal address xx7fh xx00h xx7dh external address t scinc t hcinc cntinc counter 007fh xx7dh xx00h cntint t scint t rcint t ch2 t cl2 t cyc2 clk p1 t ch2 t cl2 t cyc2 clk p2 fffe t sa t ha a n+3 a n a n+1 a n+2 port-1 address a m a m+4 a m+1 fffe a m+3 port-2 address int p2 t sa t ha t sint t rint
cy7c0430v preliminary 21 table 1. read/write and enable operation (any port) [40, 41, 42] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 17 operation x h x x high-z deselected x x l x high-z deselected x l h l d in write l l h h d out read h x l h x high-z outputs disabled table 2. address counter and counter-mask register control operation (any port) [40, 43, 44] clk mrst cntrst mkld cntld cntinc cntrd mkrd mode operation x l x x x x x x master- reset counter/address register reset and mask register set (resets entire chip as per reset state table) h l x x x x x reset counter/address register reset h h l x x x x load load of address lines into mask register h h h l x x x load load of address lines into counter/address register h h h h l x x incre- ment counter increment h h h h h l x read- back readback counter on address lines h h h h h h l read- back readback mask register on address lines h h h h h h h hold counter hold notes: 40. ? x ? = ? don ? t care, ? ? h ? = v ih , ? l ? = v il . 41. oe is an asynchronous input signal. 42. when ce changes state, deselection and read happen after one cycle of latency. 43. ce 0 = oe = v il ; ce 1 = r/w = v ih . 44. counter operation and mask register operation is independent of chip enables.
cy7c0430v preliminary 22 master reset the quadport undergoes a complete reset by taking its mas- ter reset (mrst ) input low. the master reset input can switch asynchronously to the clocks. a master reset initializes the internal burst counters to zero, and the counter mask reg- isters to all ones (completely unmasked). a master reset also forces the mailbox interrupt (int ) flags and the counter inter- rupt (cntint ) flags high, resets the bist controller, and takes all registered control signals to a deselected read state [45] . a master reset must be performed on the quadport after power-up. interrupts the upper four memory locations may be used for message passing and permit communications between ports. ta bl e 3 shows the interrupt operation for all ports. for the 1-meg quadport, the highest memory location ffff is the mailbox for port 1, fffe is the mailbox for port 2, fffd is the mailbox for port 3, and fffc is the mailbox for port 4. ta bl e 3 shows that in order to set port 1 int p1 flag, a write by any other port to address ffff will assert int p1 low. a read of ffff loca- tion by port 1 will reset int p1 high. when one port writes to the other port ? s mailbox, the interrupt flag (int ) of the port that the mailbox belongs to is asserted low. the interrupt is reset when the owner (port) of the mailbox reads the contents of the mailbox. the interrupt flag is set in a flow-through mode (i.e., it follows the clock edge of the writing port). also, the flag is reset in a flow-through mode (i.e., it follows the clock edge of the reading port). each port can read the other port ? s mailbox without resetting the interrupt. if an application does not require message pass- ing, int pins should be treated as no-connect and should be left floating. when two ports or more write to the same mailbox at the same time int will be asserted but the contents of the mailbox are not guaranteed to be valid. note: 45. during master reset the control signals will be set to a deselected read state: ce 0i = lbi = ubi = r/w i = mkldi = mkrdi = cntrdi = cntrsti = cntldi = cntinci = v ih ; ce 1i = v il. the ? i ? suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals. table 3. interrupt operation example port 1 port 2 port 3 port 4 function a 0p1 ? 15p1 int p1 a 0p2 ? 15p2 int p2 a 0p3 ? 15p3 int p3 a 0p4 ? 15p4 int p4 set port 1 int p1 flag x l ffff x ffff x ffff x reset port 1 int p1 flag ffff h x x x x x x set port 2 int p2 flag fffe x x l fffe x fffe x reset port 2 int p2 flag x x fffe h x x x x set port 3 int p3 flag fffd x fffd x x l fffd x reset port 3 int p3 flag x x x x fffd h x x set port 4 int p4 flag fffc x fffc x fffc x x l reset port 4 int p4 flag x x x x x x fffc h
cy7c0430v preliminary 23 address counter control operations counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. a port ? s burst counter is loaded with the port ? s counter load pin (cntld ). when the port ? s counter increment (cntinc ) is asserted, the address counter will increment on each low to high transition of that port ? s clock signal. this will read/write one word from/into each successive address location until cntinc is deasserted. depending on the mask register state, the counter can address the entire memory array and will loop back to start. counter reset (cntrst ) is used to reset the burst counter (the mask register value is unaffected). when using the counter in readback mode, the internal address val- ue of the counter will be read back on the address lines when counter readback signal (cntrd ) is asserted. figure 1 pro- vides a block diagram of the readback operation. ta bl e 2 lists control signals required for counter operations. the signals are listed based on their priority. for example, master reset takes precedence over counter reset, and counter load has lower priority than mask register load (described below). all counter operations are independent of chip enables (ce 0 and ce 1 ). when the address readback operation is performed the data i/os are three-stated (if ces are active) and one-clock cycle (no-operation cycle) latency is experienced. the address will be read at time t ca2 from the rising edge of the clock following the no-operation cycle. the read back address can be either of the burst counter or the mask register based on the levels of counter read signal (cntrd ) and mask register read signal (mkrd ). both signals are synchronized to the port's clock as shown in ta bl e 2 . counter read has a higher priority than mask read. addr. read back counter/ address register clk cntld = 1 cntinc = 1 cntrst = 1 mkld = 1 mkrd cntrd memory array mask register read back register bidirectional address lines figure 1. counter and mask register read back on address lines
cy7c0430v preliminary 24 counter-mask register the burst counter has a mask register that controls when and where the counter wraps. an interrupt flag (cntint ) is assert- ed for one clock cycle when the unmasked portion of the counter address wraps around from all ones (cntinc must be asserted) to all zeros. the example in figure 2 shows the counter mask register loaded with a mask value of 003f un- masking the first 6 bits with bit ? 0 ? as the lsb and bit ? 15 ? as the msb. the maximum value the mask register can be loaded with is ffff. setting the mask register to this value allows the counter to access the entire memory space. the address counter is then loaded with an initial value of xxx8. the ? blocked ? addresses (in this case, the 6th address through the 15th address) are loaded with an address but do not increment once loaded. the counter address will start at address xxx8. with cntinc asserted low, the counter will increment its internal address value till it reaches the mask register value of 3f and wraps around the memory block to location xxx0. therefore, the counter uses the mask-register to define wrap-around point. the mask register of every port is loaded when mkld (mask register load) for that port is low. when mkrd is low, the value of the mask register can be read out on address lines in a manner similar to counter read back op- eration (see table 2 for required conditions). when the burst counter is loaded with an address higher than the mask register value, the higher addresses will form the masked portion of the counter address and are called blocked addresses. the blocked addresses will not be changed or af- fected by the counter increment operation. the only exception is mask register bit 0. it can be masked to allow the address counter to increment by two. if the mask register bit 0 is loaded with a logic value of ? 0, ? then address counter bit 0 is masked and can not be changed during counter increment operation. if the loaded value for address counter bit 0 is ? 0, ? the counter will increment by two and the address values are even. if the loaded value for address counter bit 0 is ? 1, ? the counter will increment by two and the address values are odd. this oper- ations allows the user to achieve a 36-bit interface using any two ports, where the counter of one port counts even address- es and the counter of the other port counts odd addresses. this even-odd address scheme stores one half of the 36-bit word in even memory locations, and the other half in odd mem- ory locations. cntint will be asserted when the unmasked portion of the counter wraps to all zeros. loading mask regis- ter bit 0 with ? 1 ? allows the counter to increment the address value sequentially. ta b l e 2 groups the operations of the mask register with the operations of the address counter. address counter and mask register signals are all synchronized to the port's clock clk. master reset (mrst ) is the only asynchronous signal listed on ta b l e 2 . signals are listed based on their priority going from left column to right column with mrst being the highest. a low on mrst will reset both counter register to all zeros and mask register to all ones. on the other hand, a low on cntrst will only clear the address counter register to zeros and the mask register will remain intact. there are four operations for the counter and mask register: 1. load operation: when cntld or mkld is low, the ad- dress counter or the mask register is loaded with the ad- dress value presented at the address lines. this value rang- es from 0 to ffff (64k). the mask register load operation has a higher priority over the address counter load opera- tion. 2. increment: once the address counter is loaded with an ex- ternal address, the counter can internally increment the ad- dress value by asserting cntinc low. the counter can 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h h l 11 0 ? s 1 0 1 0 1 01 00 x ? s 1 x 0 x 0 x0 11 x ? s 1 x 1 x 1 x1 00 x ? s 0 x 0 x 0 x0 blocked address counter address mask register bit-0 address counter bit-0 cntint example: load counter-mask register = 3f load address counter = 8 max address register max + 1 address register figure 2. programmable counter-mask register operation [46] note: 46. the ? x ? in this diagram represents the counter upper-bits.
cy7c0430v preliminary 25 address the entire memory array (depend on the value of the mask register) and loop back to location 0. the incre- ment operation is second in priority to load operation. 3. readback: the internal value of either the burst counter or the mask register can be read out on the address lines when cntrd or mkrd is low. counter readback has higher priority over mask register readback. a no-operation delay cycle is experienced when readback operation is per- formed. the address will be valid after t ca2 (for counter readback) or t cm2 (for mask readback) from the following port's clock rising edge. address readback operation is in- dependent of the port's chip enables (ce 0 and ce 1 ). if ad- dress readback occurs while the port is enabled (chip en- ables active), the data lines (i/os) will be three-stated. 4. hold operation: in order to hold the value of the address counter at certain address, all signals in ta bl e 2 have to be high. this operation has the least priority. this operation is useful in many applications where wait states are needed or when address is available few cycles ahead of data. the counter and mask register operations are totally indepen- dent of port chip enables. ieee 1149.1 serial boundary scan (jtag) and memory built-in-self-test (mbist) the cy7c0430v incorporates a serial boundary scan test ac- cess port (tap). this port operates in accordance with ieee standard 1149.1-1900. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 3.3v i/o logic levels. it is composed of three input connections and one output connection required by the test logic defined by the standard. memory bist circuitry will also be controlled through the tap interface. all mbist instructions are compliant to the jtag standard. an external clock (clkbist) is provided to allow the user to run bist at speeds higher than 100 mhz. clkbist is multiplexed internal- ly with the ports clocks during bist operation. disabling the jtag feature it is possible to operate the quadport without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are in- ternally pulled up and may be unconnected. they may alter- nately be connected to vdd through a pull-up resistor. tdo should be left unconnected. clkbist must be tied low to disable the mbist. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) - test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the regis- ters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruc- tion that is loaded into the tap instruction register. for infor- mation on loading the instruction register, see the tap con- troller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state dia- gram (fsm)). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any reg- ister. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the quadport and may be performed while the device is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap r egisters registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the quadport test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register four-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in the following jtag/bist con- troller diagram. upon power-up, the instruction register is load- ed with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain devices. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the quadport with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the quadport. the boundary scan register is loaded with the contents of the qp input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, and sam- ple/preload instructions can be used to capture the con- tents of the input and output ring.
cy7c0430v preliminary 26 identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the quadport and can be shifted out when the tap con- troller is in the shift-dr state. the id register has a vendor code and other information described in the identification reg- ister definitions table. tap instruction set sixteen different instructions are possible with the 4-bit instruc- tion register. all combinations are listed in ta bl e 6 , instruction codes. seven of these instructions (codes) are listed as re- served and should not be used. the other nine instructions are described in detail below. the tap controller used in this quadport is fully compliant to the 1149.1 convention. the tap controller can be used to load address, data or control signals into the quadport and can preload the input or output buffers. the quadport implements all of the 1149.1 instructions except intest. ta b l e 6 lists all instructions. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap control- ler needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be exe- cuted whenever the instruction register is loaded with all 0s. ex- test allows circuitry external to the quadport package to be tested. boundary-scan register cells at output pins are used to apply test stimuli, while those at input pins capture test results. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap con- troller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. high-z the high-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all quadport outputs into a high-z state. sample / preload sample / preload is a 1149.1 mandatory instruction. when the sample / preload instructions loaded into the instruction register and the tap controller in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the quadport clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will under- go a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the quadport signal must be stabi- lized long enough to meet the tap controller's capture set-up plus hold times. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. if the tap controller goes into the update-dr state, the sampled data will be updated. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advan- tage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. clamp the optional clamp instruction allows the state of the signals driven from quadport pins to be determined from the bound- ary-scan register while the bypass register is selected as the serial path between tdi and tdo. clamp controls boundary cells to 1 or 0. runbist runbist instruction provides the user with a means of run- ning a user-accessible self-test function within the quadport as a result of a single instruction. this permits all components on a board that offer the runbist instruction to execute their self-tests concurrently, providing a quick check for the board. the quadport mbist provides two modes of operation once the tap controller is loaded with the runbist instruction: non-debug mode (go-nogo) the non-debug mode is a go-nogo test used simply to run bist and obtain pass-fail information after the test is run. in addition to that, the total number of failures encountered can be obtained. this information is used to aid the debug mode (explained next) of operation. the pass-fail information and failure count is scanned out using the jtag interface. an mbist result register (mrr) will be used to store the pass-fail results. the mrr is a 25-bit register that will be con- nected between tdi and tdo during the internal scan (int_scan) operation. the mrr will contain the total number of fail read cycles of the entire mbist sequence. mrr[0] (bit 0) is the pass/fail bit. a ? 1 ? indicates some type of failure oc- curred, and a ? 0 ? indicates entire memory pass. in order to run bist in non-debug mode, the 2-bit mbist con- trol register (mcr) is loaded with the default value ? 00 ? , and the tap controller ? s finite state machine (fsm), which is syn- chronous to tck, transitions to run test/idle state. the entire mbist test will be performed with a deterministic number of tck cycles depending on the tck and clkbist frequency. t cyc is total number of tck cycles required to run mbist. spc is the synchronization padding cycles (4 ? 6 cycles) m is a constant represents the number of read and write oper- ations required to run mbist algorithms (31,195,136). t cyc t cyc clkbist [] t c yc t ck [] -------------------------------------------- mspc + =
cy7c0430v preliminary 27 once the entire mbist sequence is completed, supplying ex- tra tck or clkbist cycles will have no effect on the mbist controller state or the pass-fail status. debug mode with the runbist instruction loaded and the mcr loaded with the value of ? 01 ? , and the fsm transitions to run_test/idle state, the mbist goes into runbist-debug mode. the debug mode will be used to provide complete fail- ure analysis information at the board level. it is recommended that the user runs the non-debug mode first and then the de- bug mode in order to save test time and to set an upper bound on the number of scan outs that will be needed. the failure data will be scanned out automatically once a failure occurs using the jtag tap interface. the failure data will be repre- sented by a 100-bit packet given below. the 100-bit memory debug register (mdr) will be connected between tdi and tdo, and will be shifted out on tdo, which is synchronized to tck. figure 3 is a representation of the 100-bit mdr packet. the packet follows a 2-bit header that has a logic ? 1 ? value, and represents two tck cycles. mdr[97:26] represent the bist comparator values of all four ports (each port has 18 data lines). a value of ? 1 ? indicates a bit failure. the scanned out data is from msb to lsb. mdr[25:10] represent the failing address (msb to lsb). the state of the bist controller is scanned out using mdr[9:4]. bit 2 is the test done bit. a ? 0 ? in bit 2 means test not complete. the user has to monitor this bit at every packet to determine if more failure packets need to be scanned out at the end of the bist operations. if the value is ? 0 ? then bist must be repeated to capture the next failing packet. if it is ? 1, ? it means that the last failing packets have been scanned out. a trailer similar to the header represents the end of a packet. mcr_scan this instruction will connect the memory bist control regis- ter (mcr) between tdi and tdo. the default value (upon master reset) is ? 00 ? . shift_dr state will allow modifying the mcr to extend the mbist functionality. mbist control states thirty-five states are listed in ta bl e 7 . four data algorithms are used in debug mode: moving inversion (mia), march_2 (m2a), checkerboard (cba), and unique address algorithm (uaa). only port 1 can write mia, m2a, and cba data to the memory. all four ports can read any algorithm data from the qp mem- ory. ports 2, 3, and 4 will only write uaa data. boundary scan cells (bsc) ta b l e 9 lists all quadport i/os with their associated bsc. no- tice that the cells have even numbers. every i/o has two boundary scan cells. bidirectional signals (address lines, data- lines) require two cells so that one (the odd cell) is used to control a three-state buffer. input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout. 1 1 1 1 97 99 98 p4_io(17-9) p3_io(17-9) p1_io(17-9) p2_io(17-9) p4_io(8-0) p3_io(8-0) p1_io(8-0) p2_io(8-0) a(15-0) mbist_state p/f 62 61 26 25 10 9 4 3 2 10 td figure 3. mbist debug register packet
cy7c0430v preliminary 28 tap controller state diagram (fsm) [47] note: 47. the 0/1 next to each state represents the value at tms at the rising edge of tck. test-logic reset run_test/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
cy7c0430v preliminary 29 jtag/bist tap controller block diagram 0 3 2 1 0 24 23 0 31 30 29 0 99 0 0 391 bypass register (byr) instruction register (ir) identification register (idr) boundary scan register (bsr) mbist result register (mrr) mbist debug register (mdr) tdi selection circuitry tdo tck tms ta p controller bist controller mrst memory cell clkbist mbist control register (mcr) (mux) 1 0
cy7c0430v preliminary 30 jtag timing waveform table 4. identification register definitions instruction field value description revision number (31:28) 0h reserved for version number cypress device id (27:12) c000h defines cypress part number cypress jedec id (11:1) 34h allows unique identification of quadport vendor id register presence (0) 1 indicate the presence of an id register test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov
cy7c0430v preliminary 31 table 5. scan registers sizes register name bit size instruction (ir) 4 bypass (byr) 1 identification (idr) 32 mbist control (mcr) 2 mbist result (mrr) 25 mbist debug (mdr) 100 boundary scan (bsr) 392 table 6. instruction identification codes instruction code description extest 0000 captures the input/output ring contents. places the boundary scan register (bsr) between the tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0111 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0110 places the boundary scan register between tdi and tdo. forces all quad- port output drivers to a high-z state. uses byr. clamp 0101 controls boundary to 1/0. uses byr. sample/preload 0001 captures the input/output ring contents. places the boundary scan register (bsr) between tdi and tdo. runbist 1000 invokes mbist. places the mbist debug register (mdr) between tdi and tdo. int_scan 0010 scans out pass-fail information. places mbist result register (mrr) be- tween tdi and tdo. mcr_scan 0011 presets runbist mode. places mbist control register (mcr) between tdi and tdo. reserved all other codes seven combinations are reserved. do not use other than the above. table 7. mbist control states states code state name description 000001 movi_zeros port 1 write all zeros to the qp memory using moving inversion algorithm (mia). 000011 movi_1_upcnt up count from 0 to 64k (depth of qp). all ports read 0s, then port 1 writes 1s to all memory locations using mia, then all ports read 1s. mia read0_write1_read1 (mia_r0w1r1). 000010 movi_0_upcnt up count from 0 to 64k. all ports read 1s, then port 1 writes 0s, then all ports read 0s (mia_r1w0r0). 000110 movi_1_downcnt down count from 64k to 0. mia_r0w1r1. 000111 movi_0_downcnt down count mia_r1w0r0. 000101 movi_read read all 0s. 000100 mar2_zeros port 1 write all zeros to memory using march2 algorithm (m2a). 001100 mar2_1_upcnt up count m2a_r0w1r1.
cy7c0430v preliminary 32 001101 mar2_0_upcnt up count m2a_r1w0r0. 001111 mar2_1_downcnt down count m2a_r0w1r1. 001110 mar2_0_downcnt down count m2a_r1w0r0. 001010 mar2_read read all 0s. 001011 chkr_w port 1 writes topological checkerboard data to memory. 001001 chkr_r all ports read topological checkerboard data. 001000 n_chkr_w port 1 write inverse topological checkerboard data. 011000 n_chkr_r all ports read inverse topological checkerboard data. 011001 uaddr_zeros2 port 2 write all zeros to memory using unique address algorithm (uaa). 011011 uaddr_write2 port 2 writes every address value into its memory location (uaa). 011010 uaddr_read2 all ports read uaa data. 011110 uaddr_ones2 port 2 writes all ones to memory. 011111 n_uaddr_write2 port 2 writes inverse address value into memory. 011101 n_uaddr_read2 all ports read inverse uaa data. 011001 uaddr_zeros3 port 3 write all zeros to memory using unique address algorithm (uaa). 011011 uaddr_write3 port 3 writes every address value into its memory location (uaa). 011010 uaddr_read3 all ports read uaa data. 011110 uaddr_ones3 port 3 writes all ones to memory. 011111 n_uaddr_write3 port 3 writes inverse address value into memory. 011101 n_uaddr_read3 all ports read inverse uaa data. 011001 uaddr_zeros4 port 4 write all zeros to memory using unique address algorithm (uaa). 011011 uaddr_write4 port 4 writes every address value into its memory location (uaa). 011010 uaddr_read4 all ports read uaa data. 011110 uaddr_ones4 port 4 writes all ones to memory. 011111 n_uaddr_write4 port 4 writes inverse address value into memory. 011101 n_uaddr_read4 all ports read inverse uaa data. 110010 complete test complete. table 8. mbist control register (mcr) mcr[1:0] mode 00 non-debug 01 debug 10 reserved 11 reserved table 7. mbist control states states code state name description
cy7c0430v preliminary 33 table 9. boundary scan order cell # signal name bump (ball) id 2 a0_p4 k20 4 a1_p4 j19 6 a2_p4 j18 8 a3_p4 h20 10 a4_p4 h19 12 a5_p4 g19 14 a6_p4 g18 16 a7_p4 f20 18 a8_p4 f19 20 a9_p4 f18 22 a10_p4 e20 24 a11_p4 e19 26 a12_p4 d19 28 a13_p4 d18 30 a14_p4 c20 32 a15_p4 c19 34 cntint _p4 f17 36 cntrst _p4 k18 38 mkld _p4 h18 40 cntld _p4 h17 42 cntinc _p4 g17 44 cntrd _p4 e17 46 mkrd _p4 e18 48 lb _p4 a20 50 ub _p4 b19 52 oe _p4 d17 54 r/w _p4 c16 56 ce1_p4 c18 58 ce0 _p4 c17 60 int _p4 k19 62 clk_p4 k17 64 a0_p3 l20 66 a1_p3 m19 68 a2_p3 m18 70 a3_p3 n20 72 a4_p3 n19 74 a5_p3 p19 76 a6_p3 p18 78 a7_p3 r20 80 a8_p3 r19 82 a9_p3 r18 84 a10_p3 t20 86 a11_p3 t19 88 a12_p3 u19 90 a13_p3 u18 92 a14_p3 v20 94 a15_p3 v19 96 cntint _p3 r17 98 cntrst _p3 l18 100 mkld _p3 n18 102 cntld _p3 n17 104 cntinc _p3 p17 106 cntrd _p3 t17 108 mkrd _p3 t18 110 lb _p3 y20 112 ub _p3 w19 114 oe _p3 u17 116 r/w _p3 v16 118 ce1_p3 v18 120 ce0 _p3 v17 122 int _p3 l19 124 clk_p3 m17 126 io0_p4 y15 128 io1_p4 w15 130 io2_p4 y16 132 io3_p4 w16 134 io4_p4 y17 136 io5_p4 w17 138 io6_p4 y18 140 io7_p4 w18 142 io8_p4 y19 144 io0_p3 v12 146 io1_p3 y11 148 io2_p3 w12 150 io3_p3 y12 152 io4_p3 w13 154 io5_p3 y13 156 io6_p3 v15 158 io7_p3 y14 160 io8_p3 w14 162 io0_p1 y6 164 io1_p1 w6 table 9. boundary scan order (continued) cell # signal name bump (ball) id
cy7c0430v preliminary 34 166 io2_p1 y5 168 io3_p1 w5 170 io4_p1 y4 172 io5_p1 w4 174 io6_p1 y3 176 io7_p1 w3 178 io8_p1 y2 180 io0_p2 v9 182 io1_p2 y10 184 io2_p2 w9 186 io3_p2 y9 188 io4_p2 w8 190 io5_p2 y8 192 io6_p2 v6 194 io7_p2 y7 196 io8_p2 w7 198 a0_p2 l1 200 a1_p2 m2 202 a2_p2 m3 204 a3_p2 n1 206 a4_p2 n2 208 a5_p2 p2 210 a6_p2 p3 212 a7_p2 r1 214 a8_p2 r2 216 a9_p2 r3 218 a10_p2 t1 220 a11_p2 t2 222 a12_p2 u2 224 a13_p2 u3 226 a14_p2 v1 228 a15_p2 v2 230 cntint _p2 r4 232 cntrst _p2 l3 234 mkld _p2 n3 236 cntld _p2 n4 238 cntinc _p2 p2 240 cntrd _p2 t4 242 mkrd _p2 t3 244 lb _p2 y1 246 ub _p2 w2 table 9. boundary scan order (continued) cell # signal name bump (ball) id 248 oe _p2 u4 250 r/w _p2 v5 252 ce1_p2 v3 254 ce0 _p2 v4 256 int _p2 l2 258 clk_p2 m4 260 a0_p1 k1 262 a1_p1 j2 264 a2_p1 j3 266 a3_p1 h1 268 a4_p1 h2 270 a5_p1 g2 272 a6_p1 g3 274 a7_p1 f1 276 a8_p1 f2 278 a9_p1 f3 280 a10_p1 e20 282 a11_p1 e2 284 a12_p1 d2 286 a13_p1 d3 288 a14_p1 c1 290 a15_p1 c2 292 cntint _p1 f4 294 cntrst _p1 k3 296 mkld _p1 h3 298 cntld _p1 h4 300 cntinc _p1 g4 302 cntrd _p1 e4 304 mkrd _p1 e3 306 lb _p1 a1 308 ub _p1 b2 310 oe _p1 d4 312 r/w _p1 c5 314 ce1_p1 c3 316 ce0 _p1 c4 318 int _p1 k2 320 clk_p1 k4 322 io9_p2 a6 324 io10_p2 b6 326 io11_p2 a5 328 io12_p2 b5 table 9. boundary scan order (continued) cell # signal name bump (ball) id
cy7c0430v preliminary 35 330 io13_p2 a4 332 io14_p2 b4 334 io15_p2 a3 336 io16_p2 b3 338 io17_p2 a2 340 io9_p1 c9 342 io10_p1 a10 344 io11_p1 b9 346 io12_p1 a9 348 io13_p1 b8 350 io14_p1 a8 352 io15_p1 c6 354 io16_p1 a7 356 io17_p1 b7 358 io9_p3 a15 360 io10_p3 b15 362 io11_p3 a16 364 io12_p3 b16 366 io13_p3 a17 368 io14_p3 b17 370 io15_p3 a18 372 io16_p3 b18 374 io17_p3 a19 376 io9_p4 c12 378 io10_p4 a11 380 io11_p4 b12 382 io12_p4 a12 384 io13_p4 b13 386 io14_p4 a13 388 io15_p4 c15 390 io16_p4 a14 392 io17_p4 b14 table 9. boundary scan order (continued) cell # signal name bump (ball) id
cy7c0430v preliminary ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ordering information document #: 38-00882 64k x 18 3.3v synchronous quadport sram speed (mhz) ordering code package name package type operating range 133 cy7c0430v-133bgc bg272 272-ball grid array (bga) commercial cy7c0430v-133bgi bg272 272-ball grid array (bga) industrial 100 cy7c0430v-100bgc bg272 272-ball grid array (bga) commercial CY7C0430V-100BGI bg272 272-ball grid array (bga) industrial 272-ball grid array (27 x 27 x 2.33 mm) bg272 package diagram

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